Summary

Description

<p>In 2012, the NASA Game Changing Development Program (GCDP), residing in the NASA Space Technology Mission Directorate (STMD), commissioned a High Performance Spaceflight Computing (HPSC) formulation activity to determine the value of an investment in a next-generation flight computing system.  A multi-center NASA team was established to sharpen understanding of the gap between the current state of the practice in flight computing and the actual future flight computing needs of NASA missions.  This team posed the question: “What are the paradigm shifting NASA space-based applications that drive flight computing?”  A series of workshops was conducted with personnel from NASA Johnson Space Center (JSC), NASA Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL).  These scientists, engineers and mission designers identified high priority functions, capabilities and mission scenarios from the NASA future mission set, and identified use cases that required or would take full advantage of a high performance spaceflight computing capability.  Both robotic and human spaceflight mission applications were examined.</p><p>To answer the related question: “What are the requirements imposed on flight computing by these applications?” NASA system engineers and mission personnel characterized for each use case: the nature of the computing, the environment, the criticality of the application, the system constraints, and the computing system and processor chip requirements.</p><p>Analysis of the set of use cases and derived requirements led to the insight that the drivers for future flight computing fall into three broad categories: 1) hard real-time calculations (such as vision-based algorithms for entry, descent and landing), 2) high throughput instrument data processing (such as for hyper-spectral and synthetic aperture radar – SAR), and 3) model-based reasoning techniques, such as for AI-based mission planning and fault management).  The takeaway was that there would not likely be a one-size-fits-all architectural solution.</p><p>The HPSC formulation team next evaluated extant and emerging computing architectures to determine which architectural concept would provide the most investment value to address the identified future NASA flight computing requirements.  Several architecture were examined, both COTS (commercial off-the-shelf) -based, and, where available, space-qualified or space-qualifiable versions:  Reconfigurable Computing, Graphic Processing Units (GPUs), Multi-Core, specialized processors (e.g., DSP – Digital Signal Procsssing), as well as hybrid approaches.  The study identified rad-hard general-purpose multi-core as the highest value architectural approach for NASA’s needs – not only addressing the range of flight computing requirements derived from the use cases, but providing certain architectural advantages in a flight computing system beyond the computational performance advance.</p><p>As NASA’s HPSC activity proceeded, the Air Force Research Lab (AFRL) and NASA identified significant requirements overlap and common interest in future flight computing.  An agency-level partnership emerged, which is manifesting through a joint investment in a Next Generation Space Processor (NGSP).</p><p>In 2013, under an initial risk-retirement phase, termed the Innovation Phase, AFRL and NASA issued awards via a joint solicitation to three companies:  BAE, Boeing and Honeywell.  These contractors are developing hardware architecture designs for the targeted future flight computing system based on a multi-core architecture.  NASA is also developing a set of benchmarks consistent with the broad set of NASA applications.  Some benchmarks will capture performance needs but others are for the purpose of evaluating certain system-level properties of the operational details of vendor-offered designs, such as support for energy management and fault tolerance.  These benchmarks are targeted for flight computing, and as such, are different than the more familiar computing benchmarks that are available in the ground-based supercomputing community.</p><p>The hardware architecture designs will be developed and evaluated in 2014.  Assuming a viable departure point has been achieved with sufficient risk retirement, in 2015 a three-year Development Phase will follow, to culminate in a board-level flight computing system product, incorporating a multi-core chip, with integrated real-time operating system, flight software development environment, and NASA-developed middleware to fully exploit multi-core architectural features for the benefit of the future spaceflight applications.  </p><p>NASA and AFRL intend to continue in partnership through the Development Phase, and are seeking additional programmatic partners for this national-level capability investment.</p>