Datasets / High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project


High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

Published By National Aeronautics and Space Administration

Issued oltre 9 anni ago

US
beta

Summary

Type of release
a one-off release of a single dataset

Data Licence
Not Applicable

Content Licence
Creative Commons CCZero

Verification
automatically awarded

Description

Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming (DBF) systems that are used in NASA's future radar missions. The ADC will employ a novel combination of time interleaving, high-speed bipolar technology and low-power techniques, such as the double-sampling technique, providing exceptional sampling speed of 500 MSPS,12 bits of resolution and very low, 100mW power dissipation. Ordinarily, ADC design requires large trade-offs in speed, resolution, and power consumption. The significance of this innovation is that it simultaneously provides a high-speed, high-resolution, and low-power ADC that is well ahead of the state-of-the-art. These three characteristics are needed for DBF systems that contain large ADC arrays. The power consumption of existing ADC chips prohibits implementation of large DBF arrays in space. Ridgetop's innovative design leverages newer semiconductor process technologies that combine silicon and germanium into a compound semiconductor.