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Low-Density Parity-Check (LDPC) Forward Error Correction (FEC) schemes are excellent tools in optimizing telemetry data integrity within the limited space to ground RF spectrum available for today's and tomorrow's satellite systems. All ten of the LDPC codes called out in the CCSDS Orange Book CCSDS 131.1-O-1 are potentially powerful tools for space to ground communications link optimization for future near-Earth and deep-space science and exploration missions. With this Phase I Small Business Innovation Research (SBIR), RT Logic will endeavor to inventory and understand the 10 LDPC codes defined in CCSDS 131.1-O-1, to prototype a single Field Programmable Gate Array (FPGA) based LDPC decoder that can potentially be the core of the 10 LDPC decoders, verify the FPGA prototype of the general purpose LDPC core using a comprehensive Very High-Speed Intgrated Circuit Hardware Description Language (VHDL) test suite and characterize the design for implementation into a Commerical-off-the-shelf (COTS) high data rate receiver. In Phase II, all of the 10 LDPC codes would be implemented into RT Logic's COTS high rate receiver in order to make the LDPC FEC schemes readily available to NASA, other Civil, the Department of Defense and commerical customers for use on their future space programs.